Limonchito working document, published as-is. Prices and lead times are estimates from September 2026 and change often.

Lemon — electronics revision B

Status: 2026-09-17. Owner: electronics stream. This file is the reference for rev B hardware. Where it disagrees with an older document, this file and lemon_totem.kicad_sch (regenerated from gen_kicad_sch.py) win.

0. Firmware interface (read this first)

nRF9151 GPIO port 0, VDD_GPIO = 3.4 V (TPS62849 "3V3" rail). Pin numbers are nRF9151-LACA LGA pad numbers (taken from a shipping nRF9151 design, see §9 risk 1).

Battery detection: no dedicated pin. The cell is on a keyed connector (J2) behind a P-MOSFET reverse-polarity switch. The firmware sees the cell only through AIN0 (P0.13) and the charger state through CHG_STAT (P0.14). A missing or reversed cell means the board is unpowered, so there is nothing for firmware to detect; a swapped cell simply looks like a cold boot (Battery Reg. Art. 11(8): firmware must accept any compatible cell, so no cell ID/authentication exists).

Notes for the firmware stream: 1. Accelerometer: STMicroelectronics LIS2DW12TR. SA0 and CS are tied to 3V3, so the I²C address is 0x19 (not 0x18). Tying SA0 to GND would burn ~170 µA through its internal 20 kΩ pull-up, so do not change the strap. INT2 is not connected. 2. CHG_STAT meaning changed. Rev A wired MCP73831 STAT to the GPIO with a pull-up to 3V3. That was a bug: MCP73831 STAT is a push-pull tri-state output that drives 5 V (its VDD) when charge is complete, which exceeds the nRF9151's 3.6 V GPIO limit. Rev B uses the BQ51013B CHG pin instead (open drain, 20 V tolerant, no current when the Qi receiver is unpowered). It is low whenever the lemon sits on a working charger, including after the cell is full. If firmware needs "full", populate R15/R16 and read P0.17. 3. LED: the firmware's led.c supports pwm-leds or gpio-leds. Use PWM. Standard drive is enough at 1.5 mA; do not set high drive. 4. Wake from System OFF: SQZ_A (level low) and CHG_STAT (level low), as main.c already does. ACC_INT1 can also be a SENSE wake source (level high) if ever needed.

Devicetree fragment for firmware/lemon.overlay (the electronics stream does not edit firmware; paste it there):

/ {
    aliases {
        led-hug = &led_hug;
        accel = &lis2dw12;
    };
    pwmleds {
        compatible = "pwm-leds";
        led_hug: led_hug { pwms = <&pwm0 0 PWM_MSEC(2) PWM_POLARITY_NORMAL>; };
    };
};
&pwm0 {
    status = "okay";
    pinctrl-0 = <&pwm0_lemon>;
    pinctrl-1 = <&pwm0_lemon_sleep>;
    pinctrl-names = "default", "sleep";
};
&pinctrl {
    pwm0_lemon: pwm0_lemon { group1 { psels = <NRF_PSEL(PWM_OUT0, 0, 15)>; }; };
    pwm0_lemon_sleep: pwm0_lemon_sleep { group1 { psels = <NRF_PSEL(PWM_OUT0, 0, 15)>; low-power-enable; }; };
};
&i2c2 {
    lis2dw12: lis2dw12@19 {
        compatible = "st,lis2dw12";
        reg = <0x19>;
        irq-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
        int-pin = <1>;
    };
};

1. What changed from rev A

Net BOM effect per unit (qty 500, estimates): LIS2DW12 $0.76, LED $0.09, GH connector about $0.10–0.25, AO3401A $0.03, ESD $0.05, NTC $0.03, FB1 $0.02, extra passives about $0.10, minus crystal and caps about $0.45. About +$0.9 per unit. The mating plug on the cell (GHR-02V-S + 2× SSHL-002T-P0.2) is fitted by the cell supplier, about $0.10–0.15, and is part of the cell spec (§3).

2. Missed-hug LED and light path

Part: Kingbright APHHS1005SYCK, 0402 (1.0 × 0.5 × 0.35 mm), 590 nm AlGaInP, top-emitting, wide angle. It is yellow to match the lemon; lemon-yellow PU passes 590 nm well. At 1–2 mA, Vf is about 1.8–1.9 V.

Drive: P0.15 → R13 1.0 kΩ → D1 → GND. I_max = (3.4 − 1.85) / 1000 ≈ 1.5 mA at 100 % PWM, inside the nRF9151's standard GPIO drive, so no transistor is needed. The firmware breath pattern (led.c: 12-step ramp, 50 ms steps, 1.2 s swell every 8 s) gives an equivalent on-time of 2 × Σramp/1000 × 50 ms = 486 ms per 8 s = 6.1 % duty. If prototypes are too dim, first reduce R13 to 470 Ω (3.3 mA) and enable high drive (NRF_GPIO_DRIVE_H0H1). Current then doubles; see §7.

Position (PCB coordinates, DESIGN.md frame: origin at body centre, X along the lemon): D1 at x = 10.0, y = 11.0, top side. This is the mechanical rev B position (lemon_geom.py LED_XY), where the clear rod is part of the battery hatch plate. The emitting face is 0.35 mm above the PCB top. Why this spot works electrically: - It is outside the cell footprint in the mechanical rev B layout (26 × 20 mm cell centred at (−0.5, −2.0): x −13.5…12.5, y −12…8), so a straight vertical rod clears the cell by ≥1.7 mm. - It is inside the copper boundary (x < 15) and clear of the +Y dome carrier (|x| ≤ 6.25). - R13 sits beside it (11.6, 10.0), and TP14 (LED anode) is on the bottom.

Light path requirement (the mechanical design already follows it: ROD_D 2.5, ROD_GAP 0.5, WINDOW_SKIN 0.6): - A clear rod Ø2.5–3.0 mm (clear SLA resin, PMMA or PC) runs in +Z from ≤0.5 mm above D1 to the skin window. Flat bottom face; frosted (bead-blasted) top face so it glows evenly. - Opaque around the rod inside the core (black paint or the core wall), so the whole lemon does not glow. - Skin window 0.6–0.8 mm of unpigmented or lightly pigmented PU, Ø ≥3.4 mm, or a clear PU plug. Diffuse transmission at 590 nm is plausibly 30–60 %. Check it on the first cast. It is the main visibility risk. - Keep-out on the PCB: nothing taller than 0.5 mm within 2.0 mm of D1 (the rod base). - If the mechanical design moves the rod, D1 can go anywhere on the top side outside the cell footprint with x < 14.5. Re-run gen_kicad_sch.py after changing ANCH["D1"].

3. Replaceable battery: J2, Q1 and what the cell must be

Connector J2: JST GH, BM02B-GHS-TBT (1.25 mm pitch, 2 pins, top entry, SMT, keyed, positive latch; LCSC C161690). Distributor figures give 5.75 × 4.05 mm including tabs and about 4.3 mm tall. Check against the JST drawing when you make the footprint. Mating plug on the cell: GHR-02V-S housing with SSHL-002T-P0.2 crimps (AWG 26–30). Rated 1 A, which covers modem bursts of 0.25–0.5 A. This follows production/SOURCING.md (latching GH survives repeated user swaps and drops), replacing the side-entry JST SH first considered. Top entry means the user unplugs straight up through the battery hatch.

Placement: top side, centre x = −1.0, y = 10.3, rotation 0 (pins along X). The body spans x −3.9…1.9, y 8.3…12.3. That is 0.3 mm from the cell edge (y = 8.0) and inside the hatch opening (HATCH_CLEAR). The mechanical model had (−1.0, 10.55). Rev B pulls it 0.25 mm toward the centre so the body stays ≥0.7 mm from the PCB edge where the +Y dome carrier's castellations sit (x ±6.25, y 12.2–13.0). What mechanical must provide: - about 4.3 mm connector height plus about 6 mm above it to lift the plug out (hatch open); - no hatch rib or foam over the plug latch; the user presses the latch and pulls the housing, never the wires (put this in the instructions); - cell lead length about 30–40 mm from the cell's PCM end to the plug.

Reverse polarity (Q1, R14): Q1 is an AO3401A P-FET in the + line, drain to the connector, source to VBAT+, gate 10 kΩ to GND. - Correct cell: the body diode conducts, Vgs ≈ −Vbat, the channel turns on. Drop ≤ 20 mV at a 250 mA burst. Charging current flows back through the channel. - Reversed cell, no charger: Vgs = 0 and the body diode is reverse biased. VBAT+ stays at 0 V, no current, no damage. - Reversed cell on a Qi pad (abnormal, for the IEC 62368-1 review): once the MCP73831 raises VBAT+ above Q1's threshold (about 1 V), Q1 conducts into the reversed cell and pulls VBAT+ back down. The node settles near the threshold, with the charger in pre-conditioning (10 % = 10 mA). The reversed cell is discharged at ≤10 mA until its PCM opens. Q1 dissipates ≤50 mW. The SiP and the rest of the board never see reverse voltage. Accept, and include it in the abnormal-operation tests. The keyed housing limits this to a miswired third-party cell. - D2 PESD5V0S1BL (bidirectional ±5 V) clamps ESD on the user-touchable connector. Being bidirectional, it does not conduct with a reversed 4.2 V cell. - Why the charger is not also gated on "cell present": a PCM that has tripped on over-discharge only recovers when the charger puts voltage on the pack. A "no cell, no charge" interlock stops that recovery and bricks a deeply flat lemon. The plain P-FET has no such lockout.

Battery detection: no GPIO (see §0). Cell voltage comes from AIN0. Presence follows from the board being powered. Firmware must accept any cell in spec (Art. 11(8)).

Spare-cell specification (publish it; spares required for 5 years by Art. 11(7)): Li-ion polymer 602025 (≤6.2 × 20.5 × 26 mm), 3.7 V nominal, 250–270 mAh, integrated PCM (overcharge 4.25–4.30 V, over-discharge 2.5–3.0 V, overcurrent ≥1.5 A), leads AWG 28–30, 30–40 mm, red = +, terminated in JST GHR-02V-S, pin 1 = + (red), IEC 62133-2 and UN38.3 reports, battery DoC. Charge 100 mA (0.4 C), cut-off 4.20 V.

4. Qi receiver resonant capacitors (BQ51013B + Würth 760308101214)

Datasheet inputs: - Coil 760308101214: L = 26 µH ±10 % (125 kHz), RDC 420 mΩ typ / 520 mΩ max, rated current 1.1 A, SRF 11 MHz, Ø19 × 0.8 mm, ferrite backed. - BQ51013B (TI SLUSB62D §9.2.1.2.2, from WPC v1.2 Vol. 1): C1 (series, Cs) = 1 / [(2π·fS)² · Ls′] and C2 (parallel, Cd) = 1 / [(2π·fD)² · Ls − 1/C1], with fS = 100 kHz +5 / −10 % and fD = 1 MHz ±10 %. Ls′ is measured on the WPC fixture (50 × 50 × 1 mm PC44 ferrite, dz = 3.4 mm, with the real housing and battery). Ls is free-space. Q = 2π·fD·Ls / R must be > 77. Cap rating ≥ 25 V (50 V chosen).

The lemon's coil-to-charger distance is about 3.3 mm (DESIGN.md §2), almost exactly the WPC fixture's 3.4 mm, so the fixture's Ls′ is the right number. Ls′ has not been measured (the coil datasheet gives only free-air L). For a ferrite-backed receiver coil 3.4 mm above a ferrite plate, Ls′/Ls is typically 1.05–1.15. TI's table shows 1.3–1.45 for large unshielded phone coils; a small shielded coil gains less. Design point: Ls′ = 1.08 × 26 = 28 µH.

Series cap: the ideal value at exactly 100 kHz would be 1 / [(2π·100 kHz)² · 28 µH] = 90.5 nF. The allowed window is asymmetric (90–105 kHz), so aim near 97.5 kHz for the most headroom: 1 / [(2π·97.5 kHz)² · 28 µH] = 95.2 nF → C1 = 47 nF + 47 nF = 94 nF (C7A + C7B, C0G 50 V 0805). C7C is a third parallel 0805 footprint, DNP, for trimming after measurement.

Check of fS = 1 / (2π·√(Ls′ · 94 nF)) across coil tolerance and the Ls′/Ls uncertainty:

Everything lands inside 90–105 kHz except a −10 % coil with no inductance gain at all, which is unlikely over a ferrite plate. C0G ±5 % moves fS by ±2.5 %, so the corners are marginal. Measure Ls′ on 5 coils in a real core on a prototype and trim with C7C (for example, +4.7 nF lowers fS by about 2.4 %).

Parallel cap, with Ls = 26 µH and C1 = 94 nF: C2 = 1 / [(2π·1 MHz)² · 26 µH − 1/94 nF] = 1 / (1.0265×10⁹ − 1.0638×10⁷) = 0.984 nF → C8 = 1.0 nF C0G 50 V. Check: fD = 1 / (2π·√(Ls · C1C2/(C1+C2))) = 992 kHz at 26 µH, 946 kHz at 28.6 µH, 1046 kHz at 23.4 µH, all within ±10 %. C8B is a DNP trim footprint.

Q = 2π · 1 MHz · 26 µH / 0.42 Ω = 389 (314 at RDC max), well above 77.

Other BQ51013B values (datasheet §9.2.1.2.4–7): BOOT 10 nF/50 V; CLAMP 470 nF/25 V (rev A had 10 nF); COMM 22 nF/50 V (raise to 47 nF if a pad drops communication); RECT 10 µF/25 V + 100 nF; OUT 1 µF, plus the 4.7 µF on the charger input. AD → GND (wireless only), AD-EN open, EN1/EN2 → GND.

Current limit: R_ILIM = K_IMAX / I_MAX with K_IMAX = 262 Ω·A. I_MAX = 200 mA (100 mA charge plus headroom) → 1310 Ω. R_ILIM = R1 + R_FOD = 1.10 kΩ + 196 Ω = 1296 Ω → I_MAX 202 mA, hardware limit I_ILIM = 1.2 × K_IMAX / R_ILIM ≈ 243 mA.

FOD: TI defaults are R_OS = 20 kΩ (RECT → FOD) and R_FOD = 196 Ω (FOD → GND). Certified Qi v1.2+ pads compare received with transmitted power to find foreign objects, so an uncalibrated receiver can cause false FOD trips (charging stops) or miss a coin. Run TI's FOD calibration tool on a prototype in the real housing with the chosen cradle puck, then fix R_OS/R_FOD. The layout brief asks for two series footprints for each.

TS/CTRL: NTC network per SLUSB62D Figure 8-12 (R2 = 20 k internal pull-up, R3 open, R1 = R12 in series with RT1). %V_HOT = 19.6 % → R_net = 4.876 kΩ; %V_COLD = 58.7 % → R_net = 28.43 kΩ. With RT1 = 10 k β3380 and R12 = 750 Ω: hot cut-off 50 °C (47.8–52.9 °C over the threshold spread) and cold cut-off 0 °C (−1.5…+2.5 °C). Beyond these the BQ51013B ends power transfer. RT1 sits on the PCB top under the cell (x −8, y 3), in contact through the foam tape. A 0–45 °C window cannot be reached with one NTC in this network (at R3 = open the span is already at its maximum), so 50 °C at the PCB is the compromise. The 100 mA (0.4 C) charge rate keeps self-heating low.

5. Accelerometer (U8 LIS2DW12TR)

Pinout (LGA-12, ST datasheet Table 2): 1 SCL; 2 CS → 3V3 (I2C mode); 3 SDO/SA0 → 3V3 (address 0x19); 4 SDA; 5 NC → GND; 6 GND; 7 RES → GND; 8 GND; 9 VDD → 3V3; 10 VDD_IO → 3V3; 11 INT2 open; 12 INT1 → P0.16. Decoupling: 100 nF each on VDD and VDD_IO. The datasheet's 10 µF bulk is covered by C21 on the 3V3 rail. There is no conflict with DRV2605L at 0x5A. SA0 and CS have internal pull-ups of about 20 kΩ at 3.6 V, so they are strapped high. Strapping low would cost about 170 µA each.

Position: top side at (−9.0, −8.5) (the mechanical placeholder), under the cell (0.7 mm tall, under the 1.2 mm limit). Position does not matter for pick-up detection.

6. EN 18031 hardware provisions

The layout designer must not add any debug connector, header or tag-connect footprint.

7. Power budget with the LED and accelerometer

Usable cell: 250 mAh × 0.85 = 212 mAh. Baseline from DESIGN.md §8 (eDRX 20.48 s, PSM off):

The LED only dominates when nobody picks the lemon up, and firmware stops breathing below 3.5 V (LED_CUTOFF_MV). The PWM overhead is an estimate: measure it with a PPK2 on the DK before fixing R13. If it is much higher, use gpio-leds blink mode (≈0.02 mA average).

8. Brief for the freelance PCB layout designer

Job: route the Lemon main PCB rev B, from the existing schematic and placement to fabrication and assembly files for JLCPCB Standard PCBA. Estimate 12–20 h (€600–1,200 at typical EU freelance rates). Fixed price preferred.

Inputs: lemon_totem.kicad_sch (KiCad 8, generated); gen_kicad_sch.py (the netlist source; ask us to change it instead of hand-editing the schematic); drawings/pcb_placement.csv (x/y/side/rotation, sizes, heights, MPNs); drawings/pcb_outline.dxf (44 × 26 mm superellipse, n = 3); NETLIST.md; ROUTING.md (stack-up and priorities); this document.

First tasks, before routing: 1. Replace U1 with Nordic's official nRF9151 symbol and footprint. Check every pad number in NETLIST.md against Nordic's pin table and report any mismatch. 2. Assign footprints. Map U6 (TPS62849DLCR, VSON-HR "DLC" 8) and U2 (NSIM-2-C) function-named pins to the datasheet land patterns. Check the DRV2605L DGS pin order and the BQ51013B RHL exposed-pad via pattern. 3. Create the custom footprints: J1 (2×4 grid, 2.54 mm, Ø1.0 mm pads, position 8 empty, no paste); TP8–TP15 (Ø1.0 mm, no paste); ANT1 feed/ground pads at x = 15…16; dome carrier edge pads; LRA lead pads; Qi coil lead pads next to U4.

Hard constraints: - 4 layers, 1.0 mm, JLC04161H-7628 (or JLC's current equivalent). L2 solid GND, L3 power. - Antenna keep-out x > 15 mm: no copper on any layer except the ANT1 feed. 50 Ω grounded microstrip from U1 pad 35 through the pi match (LANT/CANT1/CANT2, tight to U1) to the feed pad. Get the width from JLC's impedance calculator. - Parts under the cell (top side, x −13.5…12.5, y −12…8, mechanical rev B) must be ≤1.2 mm tall. - J2 (top-entry GH, about 4.3 mm), D1 and the dome carrier edges are fixed by the mechanical design. Move them ≤0.5 mm at most, and say so. - No debug connector, header or tag-connect footprint (EN 18031). J1 is pads only, on the bottom. - VBAT+ path J2 → Q1 → C1/FB1 → U1 pad 14: ≥0.5 mm or pours (modem bursts about 0.5 A). C2/C3 tight at pad 14, CDEC0 tight at pad 24, each with its own GND via. - Qi AC loop (L2 pads → C7A/B/C → U4 AC1/AC2, C8 across): short, ≥0.4 mm, symmetric, far from the RF section. U4 exposed pad: ≥6 vias to GND. - Two 0402 resistors in series for each of R11 (R_OS) and R8 (R_FOD), for FOD calibration. Ask us to add R8B/R11B (0 Ω) to the generator. - RT1 on top under the cell, not on a large pour that pulls heat away from the cell. - I2C, SQZ, CHG, LED and ACC_INT1 are slow. Route them last. - Light pipe: nothing taller than 0.5 mm within 2.0 mm of D1's centre on the top side. - Test pads ≥1.5 mm centre-to-centre from any part taller than 1 mm, all probed from the bottom. - TP12 (ACC_INT1) sits on the trace at the U1 end, and TP14 (LED_A) between R13 and D1, so the fixture checks prove continuity (TEST_FIXTURES.md steps 5b and 6).

Deliverables: KiCad project (sch + pcb), ERC/DRC clean against JLC rules; Gerbers, drill, JLC BOM and CPL; STEP of the assembled board (for the mechanical stream); PDF of all layers; a note listing any placement or net change. Acceptance: netlist export matches gen_kicad_sch.py; keep-outs respected; JLC DFM check passed.

9. Open risks

1. nRF9151 pad numbers come from a real third-party nRF9151 board (makerdiary nRF9151 Connect Kit schematic rev A, 2024-12-25), not Nordic's own pin table (Nordic's pages were unreachable this session). That design also shows: no external 32 kHz crystal, DEC0 4.7 µF, ENABLE driven high, SIM powered from SIM_1V8. The layout designer checks against Nordic's footprint (§8 task 1).
2. LED visibility through an 11 mm pipe, 0.8 mm PU and yellow pigment. Check on the first cast. Fallbacks: R13 470 Ω, a thinner window, a clear plug.
3. Qi tuning: Ls′ not measured yet. Trim footprints C7C/C8B exist. FOD calibration is needed with the chosen puck.
4. Connector choice depends on GH dimensions: footprint and height of BM02B-GHS-TBT to be confirmed on JST's drawing. The latch must stay reachable through the hatch.
5. 1.8 V SIM only: the nRF9151 supplies SIM_1V8. 1NCE industrial SIMs are normally 1.8/3 V (class B/C). Confirm on the card's datasheet before ordering 500.
6. Accelerometer INT1 continuity is not proven by factory accel: registering a trigger succeeds even with an open INT1 trace. TEST_FIXTURES.md adds a pad-level check. Request to the firmware stream: a factory accel irq subcommand (arm, wait for a tap, report whether INT1 fired).
7. U6 and U2 pin mapping, and the DRV2605L pin order, still need checking against datasheets (§8 task 2).
8. A reversed third-party cell on a charger is slowly discharged until its PCM opens (§3). Record it in the risk assessment.